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WinDbg with Intel Processor Trace

Alan Sguigna

August 27, 2023
3:36 pm

Here’s an example of combining WinDbg’s OS-aware debug capabilities with SourcePoint’s support for Intel Processor Trace (PT).

The Windows 7 Attack Surface

Alan Sguigna

August 20, 2023
12:20 pm

Windows 7 was End-of-Life’d on January 14, 2020, and Microsoft’s Extended Security Update (ESU) plan, available to select customers, ended on January 10, 2023. Without ongoing support, cybersecurity attacks on this older operating system are rising. Why is that, what vulnerabilities are these exposed to, and what are the mitigations employed by more current operating systems?

ASSET InterTech’s Cybersecurity Maturity Model Certification (CMMC) Compliance Initiative

Keith Stephenson

August 11, 2023
6:59 am

There has been a lot of discussion and intrigue on Cybersecurity and what to really be concerned about. As ASSET InterTech is moving towards CMMC 2.0 Level 2 Compliance, we felt that a blog would help explain Cybersecurity – what it is and what it is not – and why it is important to everyone.

What Is The Best Way For New Engineers To Learn Boundary Scan?

Michael Johnson

August 3, 2023
2:12 pm

It’s been great to reconnect with our Boundary Scan customers across the United States and Europe over the last several months discussing the new and exciting projects they have in the works. It’s also exciting to learn how our Boundary Scan product, ScanWorks, will play an integral role in the test, debug, validation, and deployment of these products. During one of these recent visits to a company that I consider a real power user of ScanWorks, the engineering manager who was participating in the meeting asked, “What is the best way for our new engineers to learn Boundary Scan?”

Semiconductor Search for Test Engineers – How about Ireland?

Glenn Woppman

August 2, 2023
5:53 am

Currently with all the CHIPS Acts that have passed globally, the semiconductor industry has the money flowing; now we need to find and grow all the technical talent. An article just published (Taipei Times, July 26) based on a study by the Semiconductor Industry Association (SIA) and Oxford Economics states the US could be short 67,000 chip workers by 2030. Per the report, the US chip industry will grow to 460,000 workers, up from 340,000 today. Great news in terms of jobs and opportunities, but where will the technical talent come from is the next challenge.

Everything You Need to Know About ScanWorks Interconnect Part 6: Boundary Scan Cell Descriptions

Michael Johnson

July 25, 2023
8:34 am

In addition to the BC_1 Boundary Scan cell type, there are more Boundary Scan cell types that can be used to create a Boundary Scan Register and implement the IEEE 1149.1 operations within a Boundary Scan device. The type(s) of Boundary Scan cell(s) implemented within a device are listed in the BSDL. Basic Cell (BC)_0 through BC_7 are the standard Boundary Scan cell types commonly found in an IEEE 1149.1 compliant Boundary Scan device. You may ask the question, “Are there more Boundary Scan cells than BC_0 through BC_7?”

Boundary Scan Description Language (BSDL) Explained

Alan Sguigna

July 2, 2023
1:15 pm

Boundary Scan Description Language (BSDL) provides a description of testability features within ICs that comply with the IEEE 1149.1 Standard (hereinafter used interchangeably with the term “JTAG”). Having a good understanding of the BSDL leads to a deeper knowledge of JTAG, that in turn grants insight into the technology behind IEEE 1687, also known as IJTAG.

CHIPS Acts have spread globally– Now where are the test engineers?

Glenn Woppman

June 5, 2023
10:21 pm

A case for investing in the education of the next generation of test engineers.

WinDbg integration with SourcePoint using EXDI over DCI/JTAG

Alan Sguigna

May 28, 2023
2:54 pm

Introduction to using WinDbg integrated with the SourcePoint JTAG-based debugger, using EXDI over DCI

IJTAG Tutorial: How BSDL, ICL, PDL, Verilog, STIL and SVF all fit together

Alan Sguigna

May 21, 2023
1:38 pm

This IEEE 1687 (IJTAG) tutorial includes a video of how the input and output files, inclusive of BSDL, ICL, PDL, STIL, Verilog and SVF, are part of a chip design flow.

WinDbg with Intel Processor Trace

The Windows 7 Attack Surface

ASSET InterTech’s Cybersecurity Maturity Model Certification (CMMC) Compliance Initiative

What Is The Best Way For New Engineers To Learn Boundary Scan?

Semiconductor Search for Test Engineers – How about Ireland?

Everything You Need to Know About ScanWorks Interconnect Part 6: Boundary Scan Cell Descriptions

Boundary Scan Description Language (BSDL) Explained

CHIPS Acts have spread globally– Now where are the test engineers?

WinDbg integration with SourcePoint using EXDI over DCI/JTAG

IJTAG Tutorial: How BSDL, ICL, PDL, Verilog, STIL and SVF all fit together

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