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I was reading a Design Guidelines document recently that nicely summarized what to watch out for when designing circuits with high-speed I/O. There are so many things that can go wrong, so careful design and accurate measurements are essential.
Programming NOR or large NAND flash devices can be done using a variety of technologies, including boundary scan (JTAG), processor-controlled test (emulation), or FPGA-controlled test. Which embedded instrument you use is a trade-off between speed, complexity and cost.
You may not be able to kick sand into the faces of those wimpy servers in the data center much longer. The wimps are on the rise, even though they wonโ€™t take over the beach any time soon.
The new Sandy Bridge E (Enthusiast) processors are a gamerโ€™s delight. With the new LGA2011 socket and X79 chipset, Intel Sandy Bridge-E series processors come with enhanced performance overclocking support. But is it worth the money?
OEMs in the telecom industry invest in verifying the performance and conformance of the high-speed interconnects off their gear. Does the same approach apply to chip-to-chip interconnects, and in other industries?
I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?
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