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Performance versus Conformance Testing

Alan Sguigna

January 22, 2012
11:38 am

OEMs in the telecom industry invest in verifying the performance and conformance of the high-speed interconnects off their gear. Does the same approach apply to chip-to-chip interconnects, and in other industries?

Your laptop – are you getting what you paid for?

Alan Sguigna

January 1, 2012
3:49 pm

Many of us got new laptops, e-readers, tablets, and other electronics toys as gifts over the holidays. But do these machines run as fast as they’re supposed to?

The Coming Crisis in Board Bring-Up

Alan Sguigna

December 4, 2011
7:18 pm

I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?

Programming devices at In-Circuit Test?

Alan Sguigna

November 6, 2011
3:02 pm

I read a very interesting article recently making the case for programming PLDs and Flash Memory at In-Circuit Test (ICT). But there may be better alternatives - see what do you think...

Debugging CATERR and other failures

Alan Sguigna

October 23, 2011
12:02 pm

The challenge of system debug on Intel (and other) systems can be huge. What new tricks are available for debugging system hangs, crashes, or application errors?

Don’t be Intrusive!

Alan Sguigna

October 8, 2011
3:48 pm

Ever heard the old saw about the guy (gal) that “went to a fight and a hockey game broke out”? I’d characterize the ongoing debate on the value and longevity of In-Circuit Test (ICT) as a bit of a brawl…

Solving Intel QuickPath Interconnect and DDR Margining Issues

Alan Sguigna

September 18, 2011
5:31 pm

This past week ASSET and Intel did a presentation at the Intel Developers Forum (IDF) on using ScanWorks to solve QPI and DDR3 margining problems.

What is P1838 3D test?

Al Crouch

August 12, 2011
5:50 pm

Although it has been in the news for quite a while, one of the methods thought to be the way to extend Moore’s Law is finally reaching the point where it may be deployed in the near future — 3D Silicon Integration…

P1838: the 3D Standard and its use with 1687

Al Crouch

August 11, 2011
2:00 pm

One of the newest IEEE Standards Committees is currently defining the P1838 3D Test Standard. The main goal of P1838 is to develop a “Per Die” Access Mechanism that becomes a “Stacked Die” Access Mechanism when the individual die are stacked into 3D silicon. Find out more…

PCT Detects Link Training Failures

Alan Sguigna

August 8, 2011
10:47 am

One of our customers was experiencing field returns when 10 Gigabit Ethernet ports started failing to pass traffic at full line rate. How could they test for these failing boards in manufacturing and prevent them from getting out to customers?

Performance versus Conformance Testing

Your laptop – are you getting what you paid for?

The Coming Crisis in Board Bring-Up

Programming devices at In-Circuit Test?

Debugging CATERR and other failures

Don’t be Intrusive!

Solving Intel QuickPath Interconnect and DDR Margining Issues

What is P1838 3D test?

P1838: the 3D Standard and its use with 1687

PCT Detects Link Training Failures

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