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The Experts weigh in on Serial-Data Link Testing

Alan Sguigna

May 14, 2011
4:49 pm

Today I read an interesting article in Electronic Design magazine about the complexity of testing third-generation serial-data technology. With comments from Agilent, Tektronix and LeCroy, the article highlights all of the problems associated with oscilloscopes, BERTs, AWGs and other “heavy-metal” products, and not surprisingly doesn’t say anything about the elegant alternative of using embedded instrumentation…

Is your laptop highly available?

Alan Sguigna

April 17, 2011
2:06 pm

Is your laptop highly available? Maybe not yet, but... The author ruminates on why he's spending his precious weekend hours troubleshooting gadgets that should work all the time.

The Limitations of ICT

Alan Sguigna

April 9, 2011
2:58 pm

Tired of that old bed-of-nails? Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.

Debugging on Steroids

Alan Sguigna

April 3, 2011
9:18 am

ScanWorks Embedded Diagnostics is embedded firmware which uses a CPU’s debug port to access a system’s architecturally visible registers, memory and I/O. See the technology and benefits behind this "debugger on steroids".

Intel x86 Design for Debug Guidelines

Alan Sguigna

March 27, 2011
12:21 pm

ScanWorks Embedded Diagnostics for x86 systems requires a connection between the embedded service processor (BMC, FPGA or other) supporting run control and the target CPU(s). The nature of these connections is described herein.

The Economics of NBT

Alan Sguigna

March 12, 2011
8:36 am

As testing with legacy equipment becomes more problematic, engineers look for better ways to improve test coverage, enhance diagnostics, and speed up test times. But an overriding consideration is the cost of test – are the new test technologies more or less expensive than older solutions like ICT?

The test stack

Alan Sguigna

February 20, 2011
9:20 am

Those of you with a telecom background are no doubt aware of the “OSI Network Model”, also known as the OSI pyramid or stack. It is a way of sub-dividing a communications system into smaller parts called layers. A layer is a collection of similar functions that provide services to the layer above it and receives services from the layer below it. A decade ago, the telecommunications test industry underwent a revolution when platforms emerged that could cover multiple layers of the OSI stack. Now, the same thing is happening in the circuit board test industry...

Testing 2nd generation Intel® Core™ microarchitecture (aka Sandy Bridge)

Alan Sguigna

January 17, 2011
4:16 pm

Some of you may have noticed Intel’s announcement this past week at CES of the new generation of desktop/mobile processors, the 2nd Generation Intel Core family. These processors are based upon a new microarchitecture at a 32nm process node. This increased level of density and functionality requires new board testing strategies...

Test coverage using multiple technologies

Alan Sguigna

January 10, 2011
9:17 pm

It is a well-known fact that manufacturing test strategies must involve a combination of inspection, structural, and functional test technologies in order to yield highest quality and minimize customer returns. But a new breed of non-intrusive, software-based technologies promises to disrupt legacy test solutions by guaranteeing the highest test coverage at the lowest cost. These technologies leverage off of the embedded instruments within silicon to achieve this goal in the following ways...

The Experts weigh in on Serial-Data Link Testing

More Problems with In-Circuit Test

Is your laptop highly available?

The Limitations of ICT

Debugging on Steroids

Intel x86 Design for Debug Guidelines

The Economics of NBT

The test stack

Testing 2nd generation Intel® Core™ microarchitecture (aka Sandy Bridge)

Test coverage using multiple technologies

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