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What is JTAG? and What is IJTAG?

Alan Sguigna

July 4, 2011
11:50 am

I’m sometimes asked how JTAG, IJTAG and boundary scan all relate to one another. Here’s a short explanation.

Drift in High-Speed I/O Circuits

Alan Sguigna

June 12, 2011
5:45 pm

With chip-to-chip interconnects now running at 8 GT/s and above, a new class of faults due to manufacturing and process drift is emerging. What are these faults and how are they detected?

IEEE P1687 and In-Circuit Test (ICT)

Alan Sguigna

June 5, 2011
9:43 am

Run IEEE P1687-based tests at ICT? I don't think so...

The Experts weigh in on Serial-Data Link Testing

Alan Sguigna

May 14, 2011
4:49 pm

Today I read an interesting article in Electronic Design magazine about the complexity of testing third-generation serial-data technology. With comments from Agilent, Tektronix and LeCroy, the article highlights all of the problems associated with oscilloscopes, BERTs, AWGs and other “heavy-metal” products, and not surprisingly doesn’t say anything about the elegant alternative of using embedded instrumentation…

Is your laptop highly available?

Alan Sguigna

April 17, 2011
2:06 pm

Is your laptop highly available? Maybe not yet, but... The author ruminates on why he's spending his precious weekend hours troubleshooting gadgets that should work all the time.

The Limitations of ICT

Alan Sguigna

April 9, 2011
2:58 pm

Tired of that old bed-of-nails? Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.

Debugging on Steroids

Alan Sguigna

April 3, 2011
9:18 am

ScanWorks Embedded Diagnostics is embedded firmware which uses a CPU’s debug port to access a system’s architecturally visible registers, memory and I/O. See the technology and benefits behind this "debugger on steroids".

Intel x86 Design for Debug Guidelines

Alan Sguigna

March 27, 2011
12:21 pm

ScanWorks Embedded Diagnostics for x86 systems requires a connection between the embedded service processor (BMC, FPGA or other) supporting run control and the target CPU(s). The nature of these connections is described herein.

The Economics of NBT

Alan Sguigna

March 12, 2011
8:36 am

As testing with legacy equipment becomes more problematic, engineers look for better ways to improve test coverage, enhance diagnostics, and speed up test times. But an overriding consideration is the cost of test – are the new test technologies more or less expensive than older solutions like ICT?

What is JTAG? and What is IJTAG?

Drift in High-Speed I/O Circuits

IEEE P1687 and In-Circuit Test (ICT)

The Experts weigh in on Serial-Data Link Testing

More Problems with In-Circuit Test

Is your laptop highly available?

The Limitations of ICT

Debugging on Steroids

Intel x86 Design for Debug Guidelines

The Economics of NBT

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