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In my earlier blog on Debugging Watchdog Timeouts I mentioned the dreaded No Trouble Found (NTF) problem. NTF is a huge cost to companies and is extremely difficult to quantify and to address. Something as simple as an errant wedding ring can cost companies millions of dollars. Let me explainโ€ฆ
For those working with the new Intelยฎ QuickPath Interconnect (QPI) high speed bus, there's a new book on the market called โ€œMastering High Performance Multiprocessor Signalingโ€ by Dave Coleman and Michael Mirmak. This will become the "Bible" on high speed buses. Here are the details...
This is the first of a series of blogs answering the question, โ€œwhat is IEEE 1687โ€. Subsequent blogs will cover the topics โ€œwho uses IEEE 1687โ€, โ€œwhat are the advantages of using IEEE 1687 (why use IEEE 1687)โ€, and โ€œhow to use IEEE 1687.โ€
Watchdog timeouts occur in crashed or hung systems when the main processor no longer sends a heartbeat to an ancillary service processor. These can occur in high- and low-end systems, anywhere from routers to servers to cell phones. Debugging them can be difficultโ€ฆ
The new Intelยฎ Xeonยฎ Processor 7500 Series (codenamed Nehalem-EX) is truly a leap forward for Intel server technology and forms the foundation for high-end clusters and supercomputers for years to come. Read our free whitepaper that explains how to validate and test these advanced platforms...
Last week iNEMI (the International Electronics Manufacturing Initiative) concluded its nine-month project investigating Built-In Self-Test (BIST). The purpose of the iNEMI Project was to develop and promote the adoption of chip BIST at the board and system level. Here's a summary of the conclusions...
Why do recent board designs need to be validated? Over the past few years we have seen a significant increase in signal speeds. In one generation of IA based boards, there was a 16x speed increase! This requires a new approach from designers and signal integrity engineers...
Many of us are responsible for validating and testing Intelยฎ-based designs. The latest Intelยฎ Xeonยฎ and Itaniumยฎ processor platforms use Intelโ€™s QuickPath Interconnect (QPI) to tie the processor and the I/O hubs together into single, dual, and multi-processor systems. This book from Intel explains their technology...
Recently I read a posting from a well-known In-circuit Test (ICT) vendor defending the use of test pads on high-speed signals. I found this message to be rather amusing, since the prevailing wisdom is to avoid these to prevent signal integrity issues. The posting went something like this...
How do test engineers quantify the amount of test coverage they get on a particular board design? Is this science or black magic? I believe itโ€™s both. One scientific innovation Iโ€™ve seen recently is the adoption of PCOLA/SOQ/FAM by iNEMI. Yeah, I know thatโ€™s a lot of letters strung together, but hereโ€™s what it means...
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