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Recently as ASSET is a 3rd party tool supporter of Xilinx FPGAs for a number of applications, I was reviewing the Xilinx community seeing a lot of users trying to use Vivado and Platform Cable USB II pod for production in-system programming with less-than-optimal results or no results at all. First, Xilinx says the Platform Cable USB II with Vivado/SDK as the UI, is to be used for prototype programming and is a design tool, not a production tool.
Finally! A publicly available board with Intel Direct Connect Interface (DCI) working out of the box. With our SourcePoint JTAG-based debugger, it is now possible to explore the inner workings of low-level firmware with all the power of CPU-hardware-assisted run-control and trace features, including Intel Processor Trace and Architectural Event Trace.
In collaboration with the UEFI Forum, Iโ€™ll be presenting Beyond Printf: Real-Time UEFI Debugging on Wednesday, October 27th, 2021 at 10am CT. Register here: https://www.brighttalk.com/webcast/18206/512103 to watch the session live, and/or later view the recorded video. What powerful new debugging and trace features exist on the latest Intel silicon? Continue reading, or watch the webinar.
For debugging firmware, print statements (โ€œprintfโ€) are often our most powerful tool: some bugs are caused by complex sequences of events that are too long and intricate to root-cause using just breakpoints and watch windows. In this article, I write about my explorations into โ€œat-speed printfโ€.
There have been numerous investigations into the use of the Performance Monitoring Counters (PMCs) for malware detection. Below is a quick survey of what Iโ€™ve read so far, as well as an investigation into using JTAG as an alternative access mechanism to traditional ring 0 or restricted OS mechanisms.
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