Bandwidth Tests Reveal Shrinking Eye Diagrams and Signal Integrity Problems
An old story compares the electronics industry’s unprecedented achievements with the automotive industry. If cars had kept pace with Silicon Valley, we could buy a vehicle with a V32 engine and capable of 10,000 mph; or a 30 pound car that gets 1,000 miles to the gallon — either one at a sticker price of less than $50!
The high-speed serdes and memory buses in today’s systems are a lot like that V32, 10,000 mph car screaming down a crowded highway with thousands of other cars. There’s not much margin for error at 10,000 mph. What if a car or a bit on a high-speed bus is going too fast? Or another is too slow? Or the one in the next lane is swerving into the wrong lane? They crash. On a high-speed bus it’s jitter, intersymbol interference (ISI) and crosstalk. And as the speed of a bus increases, the margin for error decreases and disruptions in traffic increase.
The authors of this ebook, Tim Caffee and Eric Johnson, are pioneers in the use of the Intel® IBIST embedded instrumentation architecture to validate high-speed I/O buses between chips on complex circuit boards. Download this e-book and learn why performance validation is so critical for today’s complex and ultra-fast circuits.
Summary of learning …
- Signal integrity validation in general – no more probes!
- Soft access validation from chip to chip
- Gigatransfers per second (GT/s) and Intel IBIST
- Validating high speed buses and DDR3 memory
- Eye diagram: jitter, ISI, crosstalk and more
