Advanced guidelines for board design for test (DFT) based on Boundary Scan with a focus on structural memory tests, flash programming, and FPGA configuration.

Implementing boundary scan Design for Test (DFT) guidelines adds the unique capability of accessing onboard boundary scan test resources for a non-intrusive test which provides open and short faults coverage.

This eBook will chronicle our own experiences with dealing with these problems and use a Commercial Off the Shelf (COTS) board to delve deeply into the testing. We will emphasize the testing of DDR memory both structurally and functionally.  A Design For Test (DFT) analysis of the target board starting with the System on Module (SOM) and continuing with the Carrier Card (CC) will be described.

Download this e-book and learn all there is to know of about the boundary scan JTAG (TAP) architecture and the problems it solves to create high test coverage.  Written by Dr. Ben Bennetts, a leading Design For Testability (DFT) expert who has worked for GenRad, Synopsys and LogicVision. Additional content has been added to this e-book by ASSET’s own Chief Technology Officer Adam Ley and Application Engineer Ben Bales.

As this eBook enters its 3rd edition, content has been added describing some of the latest advancements in DDR memory, power, speed, and test technology. New memory devices such as DDR5 which utilize CT mode, and Graphics Double Data Rate 5 (GDDR5) SDRAM and GDDR6 Synchronous Graphics Random Access Memory (SGRAM) devices that implement forms of boundary-scan test technology, are described herein.

This eBook is to address what ASSET is seeing with our customer base that are trying to use Xilinx tools for device programming in a production setting.

ScanWorks users can bridge the coverage gap between boundary scan and functional test via its Component action. This action allows for testing of non-boundary scan devices, such as analog to digital converters (ADCs), digital to analog converters (DACs), Ethernet PHYs, LED, switches, clocks, and other non-boundary scan devices through the PCBs boundary scan infrastructure.

The 1st edition of this eBook described DDR4 testing using CT and/or MAV actions in the production environment. For this 2nd edition, content has been added which provides an overview of DDR4 device structure, commands, and operation sequences.