IEEE 1149.1 JTAG and Boundary Scan Tutorial

JTAG was originally developed to solve board interconnect test problems and has evolved into a widespread and generic soft access test mechanism for chips, boards and systems. Examples includes reading internal registers and chip ID-codes, program flash memories, run BIST and embedded instruments thru IJTAG.

Download this e-book and learn all there is to know of about theย boundary scan JTAG (TAP) architecture and the problems it solves to create high test coverage. ย Written by Dr. Ben Bennetts, a leading Design For Testability (DFT) expert who has worked for GenRad, Synopsys and LogicVision.

This e-book will tell you about the standard and how it can be put to work in the design, verification and manufacturing process. It also provides information of JTAGโ€™s relationship with other test techniques such as In-Circuit Testing (ICT), functional test, CPU emulation and others.

Learn about …

  • JTAG, IEEE standards 1149.1, 1149.6 and 1532
  • DFT Guidelines for chips and boards
  • The TAP interface: what to test forโ€ฆand what not!
  • Boundary Scan Description Language, BSDL
  • Raising fault coverage: digital and analog
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