Platform Validation Using Intel® Interconnect Built-in Self Test | IBIST

This paper describes the empirical results of platform validation using Intel® Interconnect Built-In Self Test (IBIST) and the ScanWorks HSIO product. Among the experiments conducted were:

• Bit Error Rate (BER) testing on Intel QuickPath Interconnect (QPI)
• Effect of equalization settings on system margins
• Eye diagram variations based upon different silicon
• Static patterns versus Linear Feedback Shift Register (LFSR) pseudo-random patterns
• Effect of margin point dwell times
• Margin degradations due to concurrent I/O testing
• Compare/contrast HSIO/IBIST tests with oscilloscope results

The advantages of Intel IBIST technology versus oscilloscopes are highlighted. It is shown that system margins are highly dependent upon the on-board silicon, as well as the stress patterns, dwell time, and concurrent stress on a device.