Testing DDR4 Memory with Boundary Scan/JTAG | Second Edition
Memory test was at the top of the list of prevalent problems along with ‘loss of access to test points’ and ‘the need to perform debug/diagnostics on board failures.’ When asked which type of built-in self-test (BIST) instruments would solve the engineer’s problem, memory BIST was rated the second most needed, virtually tied with BIST instruments for validating high-speed I/O buses. Clearly, the ability to thoroughly test, characterize and diagnose problems with soldered-down memory is one of the most pressing problems in the industry. Using Double Data Rate Fourth Generation Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) memory as an example, this eBook discusses how boundary-scan test (BST) methods based on the IEEE 1149.1 standard, including the built-in Connectivity Test (CT) of DDR4 SDRAM memories and general-purpose Memory Access Verification (MAV), can be used to test and diagnose soldered-down memory devices (not to preclude use also for socketed modules, when applicable). It is assumed that a BST tool is being used to test the DDR4 SDRAM memory.
The 1st edition of this eBook described DDR4 testing using CT and/or MAV actions in the production environment. For this 2nd edition, content has been added which provides an overview of DDR4 device structure, commands, and operation sequences.
Key Points:
- Testing memories at every step in the product life cycle
- DDR4 structure and basics
- Bank Group, Bank, Row and Column
- DRAM sizing and addressing
- DRAM page size
- Accessing memory
- Command truth table
- Read operation
- Write operation
- Connectivity Test (CT) of DDR4 memories
- What is a Memory Access Verification (MAV) test?
- Boundary-scan testing of DDR4 memories
- Testing DDR4 with a boundary-scan tool
