Confidence Tests Tabs

JTAG Tab

PBD test. Run this test to determine whether the PBD is operating properly.

JTAG ID test. This test causes all the JTAG IDs to be read from the JTAG scan chain of the target. When the test ends, you can open a report that lists the IDs that were received.

JTAG pattern test. This test shifts a known pattern through the data register (DR), reads it back, and uses the return value to calculate the chain size. This is cross-checked against the results of the JTAG ID test. This is a good test for stressing the JTAG circuitry to be sure that it is working reliably.

Pattern. This pattern can be any 32-bit hexadecimal pattern. Choose a pattern and define it in the text box.

 

Confidence Tests dialog box showing the JTAG tests

Target Memory Tab

Read target memory. This reads target memory from a given start address to a given end address. The data that are read are not checked for validity. This test can be used to uncover JTAG-related memory read problems.

Write target memory. This test first writes, then reads target memory from a given start address to a given end address. The read data are checked for validity. To determine the nature of a problem, open a Memory window and view the results.

Start address/End address. Determine the range of memory you want to test. Place the start and end addresses in the appropriate text boxes.

Write Data Pattern section. This section offers the data pattern options:

• Address as Data is most useful for exposing problems with memory address lines.

• Checkerboard is useful for exposing problems with memory data signals. (The Checkerboard pattern looks like: 55555555 AAAAAAAA 55555555 AAAAAAAA.)

• Fill With:.allows you to set a data pattern. For this last option, fill in the text box with a data value. That value is then written to every memory location within the selected address range.

 

Confidence Tests dialog box showing Target Memory tests